Verilog source text files consists of the following lexical tokens:
- White Space
White spaces separate words and can contain spaces, tabs, new-lines and form feeds. Thus a statement can extend over multiple lines without special continuation characters.
- Comments
Comments can be specified in two ways ( exactly the same way as in C/C++ ):
Begin the comment with double slashes (
//). All text between these characters and the end of the line will be ignored by the Verilog compiler.Enclose comments between the characters
/* and */. Using this method allows you to continue comments on more than one line. This is good for “commenting out” many lines code, or for very brief in-line comments.
Example
a = c + d; // this is a simple single line comment
/* however, this comment continues on more
than one line this is multiline comment */
assign y = temp_reg;
assign x=ABC /* plus its compliment*/ + ABC_
- Numbers
Number storage is defined as a number of bits, but values can be specified in binary, octal, decimal or hexadecimal.
Example
3’b001, a 3-bit number
5’d30, (=5’b11110)
16‘h5ED4, (=16’d24276)
reg [15:0] x = 16'h9678
Top comments (0)